1. Field of the Invention
The present invention relates to a semiconductor device, in particular, a semiconductor memory device. More specifically, the invention relates to a semiconductor readout circuit capable of reading out data in a memory cell of a semiconductor device at a high speed.
2. Description of the Related Art
Conventionally, as nonvolatile memories that are electrically rewritable, various nonvolatile memories such as an EEPROM, a flash EEPROM (hereinafter, flash memory), an SW memory (side wall memory) where a memory cell has a electric charge keeping area at the side of a control gate, and so forth are present and disclosed. These nonvolatile memories are in common in that data is memorized into a memory cell and read out therefrom. There are various structures in memory cells, and for example, in a flash memory, a MOSFET equipped with a floating gate is used as a memory cell. In the flash memory, the threshold voltage of a transistor changes according to the electric charge accumulation condition of a floating gate of this memory cell, and this threshold value are memorized as data. When data is to be read out from the memory cell, a predetermined readout voltage is impressed via a bit line to the drain of a selected memory cell by a word line connected to the control gate of the memory cell, and the bit line connected to the drain of the memory cell, and changes in memory cell current owing to the difference in the sizes of the threshold voltage of the memory cell transistor, i.e., changes in the current of the bit line connected to the memory cell are detected and amplified by a circuit such as a sense amplifier or so, thereby data is read out.
FIG. 15 shows a memory cell readout circuit 100 according to the conventional art. In the circuit shown in FIG. 15, when a memory cell to be read out is to be selected among a memory array 104 where memory cells are arranged in array, it is selected by use of a bit line selection transistor 105 and a word line WL which is input to the memory array 104. In the circuit shown in FIG. 15, the readout circuit 100 comprises a feedback-type bias circuit 101, a load circuit 102, and a comparator circuit 103, to the memory array 104.
Operations of the readout circuit 100 shown in FIG. 15 will be briefly described hereinafter. In the case where the memory array 104 is structured by flash memory cells, by the word line WL and the bit line BL, the memory cell as a readout objective in the memory array 104 is selected. Before this selection operation, the bit line voltage is supposed to be at GND level (ground voltage). In FIG. 15, for simplicity of explanations, only one line is illustrated for each of the word line WL and the bit line BL.
When the word line WL of the memory cell to be read out is selected, and the bit line BL of the memory cell to be read out is selected by the bit line selection transistor 105, charging of the selected bit line BL is started via charging of the node N2 by the load circuit 102. When the charging of the bit line BL is carried out to a certain voltage, by the feedback-type bias circuit 101, the bit line voltage is kept at a predetermined voltage, and the voltage of the readout input node N1 is determined according to the current flowing through memory cells and the voltage-current characteristics of the load circuit 102. The voltage of the readout input node N1, with the same load circuit 102, changes according to the current flowing through memory cells. The current flowing memory cells, in the case of a flash memory, changes according to threshold voltage, therefore the voltage of the readout input node N1 changes according to the threshold voltage of the flash memory.
Among inputs of the comparator circuit 103, the reference voltage Vref with respect to the voltage of the readout input node N1 is set to a voltage at which changes in a voltage of the readout input node N1 can be judged in the comparator circuit 103. For example, the intermediate voltage between the voltages of the readout input node N1 when the threshold voltage of the memory cell is high and low resepectively is made as the reference voltage Vref.
When the threshold voltage is low and memory cell current flows, the readout input node N1 outputs a voltage which is lower than the reference voltage Vref, and when the threshold voltage is high and the memory cell current does not flow, the readout input node N1 outputs a voltage which is higher than the reference voltage Vref. As a result, by the comparator circuit 103, it is judged whether the voltage of the readout input node N1 is higher or lower than the reference voltage Vref, thereby the size of the threshold voltage of the memory cell is judged.
In a readout input node N1 as mentioned above, when the current supply capacity of the load circuit 102 is large with respect to the memory cell current, i.e., the bit line current, the voltage difference, which is output to the readout input node N1, between the voltage when the memory cell current is large and the voltage when the memory cell current is small becomes small, causing difficulty in reading data at high speed.
Accordingly, the current supply capacity of the load circuit cannot be too large. This means when the bit line capacity is large, it takes time to attain a bit line voltage preferable for readout causing the memory cell readout time being longer. However, because of the large capacity of semiconductor memory devices and the restrictions of their production costs by suppressing division of the memory array in the bit line direction, the bit line becomes long, and its capacity becomes large accordingly, therefore, there is a demand for a readout circuit which can conduct memory cell readout operations at a high speed, even when the bit line capacity is large. To solve this problem, a bit line charge circuit (hereinafter, referred to as precharge circuit) is proposed.
FIG. 16 shows an example of a memory cell readout circuit including a precharge circuit disclosed in JP-A 2000-311493. In FIG. 16, a memory cell readout circuit 110 comprises a feedback-type bias circuit 111, a load circuit 112, and a precharge circuit 113. By the way, for simplicity of explanations, only one of memory cells 115 in a memory cell is shown therein.
The operation principle of the memory cell readout circuit 110 is that a bit line BL is charged at a high speed by the precharge circuit 113 which has a sufficiently larger current supply capacity than that of the load circuit 112, and when the bit line is charged up to a certain voltage, the operation of the precharge circuit 113 is stopped, and by the load circuit 112 and the feedback-type bias circuit 111, changes of the memory cell current are converted into voltage changes in the readout input node N1, and in a comparator circuit 114, the voltage changes are compared with the reference voltage Vref, and readout operations are carried out. In the circuit example in FIG. 16, by a pulse signal which is generated on the basis of a timing signal generated by an address transition detection circuit and the like (ATDP signal), the activation period (precharge period) of the precharge circuit 113 is determined, and by the feedback bias circuit 111, the hold voltage of the bit line BL is determined. FIG. 17 shows an example of a circuit which generates an ATDP signal.
FIG. 18 shows an example of a readout circuit of the same concept as that in FIG. 16. A readout circuit 120 in FIG. 18 has a same circuit configuration as the readout circuit 100 in FIG. 15 except that it is equipped with a precharge circuit 121 which works only for a predetermined precharge period. The difference between the readout circuit 120 in FIG. 18 and the readout circuit 110 in FIG. 16 is the circuit characteristic of the feedback-type bias circuit 101. The output change ratio of the gate voltage of a transfer gate 106 comprising an N-type MOSFET to the voltage of the node N2 appears larger in the feedback-type bias circuit 101 in FIG. 18. Accordingly, the behaviors of the transfer gate 117 to the voltage of the node N2 in the readout circuit 110 in FIG. 16 correspond to that of the transfer gate 106 to the voltage of the node N2 in the readout circuit 120 in FIG. 18. The readout circuit 120 in FIG. 18, in the same manner as the readout circuit 110 in FIG. 16, carries out charging operations, up to a bit line hold voltage which is determined by the feedback-type bias circuit 101, while the precharge signal PRC of the precharge circuit 121 is at an “H” (high) level (for precharge period).
With reference to FIG. 18, suppose the operations of the N-type MOSFET of the transfer gate 106 of the feedback-type bias circuit 101. Suppose the state when bill line is charged up to the bit line hold voltage by the precharge circuit 121. When the precharge signal PRC is maintained at an “H” level after charging up to the bit line hold voltage by the precharge circuit 121, the precharge circuit 121 does not carry out the charge operations of the bit line BL. This is because when the node N2 which has the same potential as the bit line BL, is charged up to the bit line hold voltage, the voltage of the node N3 of the feedback-type bias circuit 101 reaches a certain level, and that voltage level turns an N-type MOSFET 122 of the precharge circuit 121 into an OFF state. As a result, though the precharge signal PRC is at an “H” level, the charge operations of the bit line BL by the precharge circuit 121 stop, and the bit line BL is not charged up to the bit line hold voltage or higher. Because the node N3 is connected to a gate electrode of the transfer gate 106, the transfer gate 106 is also turned OFF. Strictly speaking, in the charge route of the precharge circuit 121, there exists ON resistance of an N-type MOSFET 123 to whose gate the precharge signal PRC is input, therefore the voltage between the gate and the source of the N-type MOSFET 122 of the precharge circuit 121 is different from the voltage between the gate and the source of the transfer gate 106 of the feedback-type bias circuit 101, and conditions are slightly difference between the OFF state of the N-type MOSFET 122 and the OFF state of the transfer gate 106, nevertheless, the transfer gate 106 is in an OFF state.
This state is the state where the charge of the bit line BL is completed. When the operation of the precharge circuit 121 is stopped, in the case when the threshold voltage of the memory cell selected by the bit line selection transistor 105 is low, and in the case when the word line connected to the memory cell is selected, the charge level of the bit line BL is lowered by the memory cell voltage. Namely, the voltage of the node N2 falls. As the voltage of the node N2 falls, the voltage of the node N3 which is the gate input of the transfer gate 106 rises, and the transfer gate 106 shifts from an OFF state to an ON state. As a result, the readout input node N1 changes into the voltage which is determined by the current which flows when the transfer gate 106 is turned into an ON state, and the load current that the load circuit 102 flows. As an example of the load circuit 102, as shown in FIG. 19, there is a load circuit which uses a P-type MOSFET which uses a predetermined bias voltage as gate voltage.
Next, how the voltage of the readout input node N1 is determined by the cell current which changes according to the difference of the threshold voltage of the memory cell and the load current of the load circuit 102 will be described with reference to FIG. 20. In FIG. 20, the current-voltage characteristic of the load circuit using the P-type MOSFET is shown in (a), and the current-voltage characteristic in the state where the transfer gate 106 is in an ON state (the state where the threshold voltage of the memory cell is low, and the cell current is large) is shown in (b), and the current-voltage characteristic in the state where the transfer gate 106 is roughly in an OFF state (the state where the threshold voltage of the memory cell is high, and the cell current is small) is shown in (c). The DC voltage VN1L of the readout input node N1 in the case when the threshold voltage of the memory cell determined by the characteristic (a) and the characteristic (b) is low, is given by the voltage value at the cross point of the characteristic (a) and the characteristic (b). Therefore, when the threshold voltage of the selected memory cell is low, the readout input node N1 shifts from the level at completion of precharge of the bit line BL to the voltage VN1L.
On the other hand, when the threshold voltage of the selected memory cell is high, the current which flows from the bit line BL to the memory cell is small, and the voltage level of the node N2 hardly falls, and the transfer gate 106 remains in an almost OFF state (or in a slightly ON state). The DC voltage VN1H of the readout input node N1 in the case when the threshold voltage of the memory cell determined by the characteristic (a) and the characteristic (c) is high, is given by the voltage value at the cross point of the characteristic (a) and the characteristic (c). Therefore, when the threshold voltage of the selected memory cell is high, the readout input node N1 shifts from the level at completion of precharge of the bit line BL to the voltage VN1H. As shown in FIG. 20, when the current-voltage characteristic of the load circuit 102 is characterized as shown in (a) of FIG. 20, the readout input node N1 appropriately changes according to the threshold voltage of the memory cell.
In the DC load circuit using such a P-type MOSFET as shown in FIG. 19, though the bit line charge is complete, the operation of the precharge circuit 121 is continued. The voltage of the bit line BL is maintained at the bit line hold voltage, but, because the transfer gate 106 of the feedback-type bias circuit 101 is in a roughly OFF state, the readout input node N1 is charged by the load circuit, and the voltage thereof rises higher than the voltage at completion of the bit line charge. If the transfer gate 106 is being OFF state for a long time after the precharge circuit 121 starts operating and the bit line charge is complete, the voltage of the readout input node N1 rises to the maximum power source voltage. Thereafter, the operation of the precharge circuit is stopped, and when the threshold voltage of the selected memory cell is low and the bit line current starts flowing according to the memory cell condition, the voltage of the readout input node N1 changes to the voltage VN1L. However, once the voltage of the readout input node N1 rises near the power source voltage, in some cases, the readout input node N1 does not change rapidly to the voltage VN1L. For example, in a large capacity memory, the bit line length is long so as to make the chip size small, as a result, its bit line resistance and bit line capacity become large. Accordingly, even when the transfer gate 106 is turned into an ON state, because the bit line resistance and the bit line capacity are large, it takes time to shift to the voltage VN1L.
In FIGS. 21 and 22, examples of the comparators 103 are shown. In FIG. 21, a differential amplifier using an N-type MOSFET as an input device is used as a comparator circuit, while in FIG. 22, a differential amplifier using a P-type MOSFET as an input device is used as a comparator circuit. In both comparators in FIGS. 21 and 22, when the input voltage is input near the power source voltage, even if there is a voltage difference between the reference voltage Vref and the voltage of the readout input node N1, output is not carried out at a high speed. For example, in FIG. 21, because the voltage between the gate and the source of the N-type MOSFET at the input stage is too large, the amplification ratio falls. Further, in FIG. 22, the gate source voltage of the P-type MOSFET at the input stage becomes below the threshold voltage, and the P-type MOSFET becomes an OFF state. As for the bias in FIGS. 21 and 22, the voltage value is not necessarily the same, and is different from the voltage value of the bias of the load circuit in FIG. 19.
In order to make the output of the comparator circuit 103 shown in FIG. 18 carried out at high speed, the input voltage of the comparator circuit 103 needs to be at optimized voltage with which comparator circuits can operate at high speed. However, in the readout circuit 120 in FIG. 18, after completion of the charge of the bit line BL, if the operation of the comparator circuit 103 is continued, the voltage of the readout input node N1 will rise by the load circuit 102. In order to make the readout input node N1 at he optimized voltage for the comparator circuit 103, after completion of the charge of the bit line, when the readout input node N1 reaches the optimized voltage, the operation of the precharge circuit 121 may be stopped. For example, when the operation timing of the precharge circuit 121 is stopped by a pulse signal ATDP generated by an inverter delay circuit or the like on the basis of the signal generated by an address transition detection circuit shown in FIG. 17, it has been difficult to realize an appropriate timing in consideration for the operation voltage range, the operation temperature range and fluctuations in manufacturing processes. This is because there is no causal relationship between the increase in voltage of the readout input node N1 and the pulse signal ATDP of an inverter delay circuit as shown in FIG. 17, and the pulse signal ATDP is not a signal which stops the operation of the precharge circuit 121 even when the readout input node N1 reaches a predetermined voltage.
A method to solve the above problem is disclosed in FIG. 3 of JP-A 2000-311493. The circuit thereof is shown in FIG. 23. A memory cell readout circuit 130 shown in FIG. 23, in comparison with the memory cell readout circuit 110 in FIG. 16, is equipped with a second transfer gate 131 comprising an N-type MOSFET which short-circuits between the readout input node N1 and a gate node N3 of a transfer gate 117 of a feedback-type bias circuit 111. After completion of the bit line charge, even when the voltage of the readout input node N1 starts rising, while an EQL signal is at an “H” level, the voltage of the gate node N3 of the transfer gate 117 is forcibly increased by the second transfer gate 131, and the transfer gate 117 is turned into an ON state, thereby unnecessary voltage increase of the readout input node N1 is prevented. However, in this method using the EQL signal, if the pulse width of the EQL signal is too short, a pulse itself may disappear owing to the resistance and capacity of wires and the like, and if the pulse width is long, readout time may become long accordingly.